A semiconductor integrated circuit is wired according to a predetermined wiring rule and, when multiple layers are wired, they are connected through vias (also called a through hole). In such wiring, a wire (called wide wire) wider than other signal wires (called fine wires) is usually used for the power wire and the ground wire to reduce the effect of a voltage drop. A wide wire is also used in many cases for a signal wire, such as a clock signal wire or other output signal wire where the driving power is required, to reduce a reduction in the signal level. In wiring such a wide wire, a space to the neighboring wires must be set wide.
One of the reasons is that a sufficient space (margin) to the neighboring wires is required to allow for a tolerance in the wire width of a wide wire. Another reason is a processing reason that occurs when a wiring pattern is formed on a semiconductor substrate because a wide pattern affects the other parts of the wiring pattern on a semiconductor substrate at exposure time during the fabrication of the semiconductor integrated circuit. Because a wider wire increases an exposure patterning error, the space is set wider. This is a well-known fact in designing and fabcticating a sub-micron semiconductor integrated circuit.
A still another reason is the dishing problem during Chemical Mechanical Polishing (CMP). Also related to a wide wire is fluid erosion (hydro-abrasion). As the wire becomes wider, the amount of dishing of the wiring metal part becomes larger at polishing time (i.e. after polishing) and, if the silicon oxide part that is a wiring space part is small, the amount of dishing becomes extremely large. This is a reason for increasing the space.
The following describes dishing and erosion with reference to FIG. 8. Because copper (Cu) is eroded by erosion more easily than silicon dioxide (SiO2), the polishing surface at CMP time tends to be lowered as the ratio of the Cu area becomes higher as shown in FIG. 8A. Because copper (Cu) is eroded more easily than SiO2, the polishing surface at CMP time tends to be lowered as the Cu area becomes larger and the amount of dishing becomes large as shown in FIG. 8B. In addition, because the surface is eroded by erosion when the wiring space of a wide wire is narrow, the SIO2 part between the Cu parts is not almost resistant to the scraping by CMP as shown in FIG. 8C. In contrast, when the wiring space of a wide wire is expanded, the surface is slightly scraped by erosion as shown in FIG. 8(d) and, therefore, the intermediate SIO2 part reduces the amount of scraping by CMP.
On the other hand, just as the space to a wide wire must be set wide when the above-described wiring pattern is formed, it is well known that, when vias for connecting different wiring layers are provided densely, the space between vias must be set wide. For vias, note that two-dimensional density has more influence than one-dimensional density. Thus, for two-dimensional density, a criterion different from that of wiring should be prepared for spacing.
When designing the arrangement of those vias, a connecting macro, where multiple vias are arranged at a space (interval) between each two vias according to the area of the intersection between anticipated wide wires, is provided for connection. For example, as shown in FIG. 9, a macro where 3×3 vias are arranged at intervals between them is used to connect the wide wires in the upper layer to the wide wires in the lower layer. In this example, the minimum spaces SV100 and SV101 in the x-axis and y-axis directions are set differently to prevent two-dimensional density.
A method for easily and reliably determining a location where vias are dense is disclosed, for example, in Patent Document 1. Patent Document 1 describes that the two-dimensional via density described above has more problems than the one-dimensional via density.
Patent Document 2 discloses a related technology. This document discloses a layout design method and a design program that allow the wiring space to be varied according to the potential difference between wires considering oozed copper caused by the electric field between copper wires.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2002-183238A
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2003-31664A